Publication: Design and simulation of high efficiency multiplier for biomedical application
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Date
2024-07
Authors
Ku, Kai Yi
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Abstract
This work presents a comparative analysis of low-power Very Large Scale Integration (VLSI) multipliers, focusing on three distinct methodologies: Array,
Wallace Tree, and Booth multipliers. The critical need for fast and energy-efficient multipliers in various domains, particularly in biomedical applications, prompted this investigation. The study includes a detailed examination of each multiplier's performance characteristics, emphasizing aspects such as delay reduction, lower power consumption, and reduced area consumption. The physical verification of all their substitute blocks was performed to prove their capability and suitability as a multiplier and to enhance low power through the size of the transistor. The design of multipliers to improve the production of the complex circuit and the analysis of the multiplier are resolved by the partial product reduction. All the designs and simulations will be carried out on Cadence Virtuoso® based on SilTerra 180 nm technology process. These structural multipliers are thoroughly compared. Among the three multipliers, the Wallace Tree multiplier was found to have the highest speed and the smallest area footprint, while the Booth multiplier could be preferable for applications requiring reduced power consumption.