Publication: Design and post layout simulation of the single-ended folded cascode low noise amplifier
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Tee, Chee Keong | |
| dc.date.accessioned | 2024-08-05T02:36:50Z | |
| dc.date.available | 2024-08-05T02:36:50Z | |
| dc.date.issued | 2008-05-01 | |
| dc.description.abstract | W-CDMA (Wideband Code Division Multiple Access) is a type of popular 3G cellular network. Wireless receivers for W-CDMA application need to be able to detect and amplify incoming low-power signals without adding much noise. The most common solution uses low noise amplifier (LNA) as the first stage in receiver. The strict requirement of good blocks performance in the W-CDMA receiver has motivated studies on feasibility of CMOS technology for the implementation of good noise performance in the LNA. The advancement in the CMOS technology has made it possible to integrate the whole system on a single chip. This project focused on designed and post-layout simulation of single-ended folded cascode CMOS LNA using a standard 0.18 μm fabrication process. In this project, the folded-cascode LNA was following the Power-Constrained Simultaneous Noise and Input Matching (PCSNIM) technique with an additional capacitor, Cex connected from gate to source of a common source transistor and employed inductive source degeneration termination. Furthermore, this technique helps on-chip input matching. Pre-layout simulation results shows that CMOS technology has the capability to achieve a 0.6V power supply while achieves a power gain S21 of 14.8dB , input reflection coefficient, S11 of -11.4dB , output reflection coefficient, S22 of -21.8dB, reverse isolation, S12 of -44.75dB and NF of 2.0 dB. Linearity on Input Third-Order Intercept Point (IIP3) is -11.81dBm extrapolated at -30dBm and Input 1dB Compression Point (P1dB) is -25.9dBm. Total power consumption is 2.35mW. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/20029 | |
| dc.language.iso | en | |
| dc.title | Design and post layout simulation of the single-ended folded cascode low noise amplifier | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |