Publication: Low power 8t dual port register file design using 65nm process technology
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Date
2007-03-01
Authors
Omar, Noor Fadillah
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Abstract
This thesis describes a low power 8T dual port register file design using 65nm process technology. This SRAM architecture consists of many iterative blocks – memory array, I/O blocks and driver blocks. The memory capacity is 2Kbyte with 128x128 bit organization and is designed using 65nm process technology. The operational frequency is 500MHz. The memory cell is constructed using eight transistors that has separate port for write and read operation. This allows read and write operation to occur simultaneously within one clock cycle at different address. The main objective of this project is to find the circuit techniques to reduce the total power consumption- active, standby and leakage power. First, the simulation is run to identify the blocks that consume most power during those three modes of operation. Analyzing the root causes of the high power consumption from respective blocks, some circuit techniques have been introduced to decrease the power number. The priority is the leakage power, and then the standby, finally will be the active power. The techniques are power gating, forced stacked, clamped transistor, NMOS pull-up and increased length. This SRAM architecture was simulated using Cadence Analog Artist, Cougar Lynx simulator to verify the read, write operation, and get the current profiling of each block. As the conclusion, the total leakage power reduction from those four circuit implementations is 26%. The standby power reduction is 4%. Lastly, the active power is less by 7%.