Publication: Comparative study of the crosstalk mitigation techniques for ddr5 on the overall impact in the signal integrity area
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Date
2023-08
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Comparative study of the crosstalk mitigation techniques for ddr5 on the overall impact in the signal integrity area
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Abstract
Due to the development of high-speed DDR5, frequency rate doubling in DDR4 for 3.2GHz, the crosstalk issue has been expanded. Crosstalk noise suppression
is crucial in DDR5, which dictates weak coupling between transmission lines over a wide band. To understand the effects of crosstalk mitigation techniques performance, six different kinds of design topologies are designed, simulated, discussed and compared. The simulation test structures are characterised at high-frequency (up to 20 GHz) with scattering parameters using a frequency-based 3D modelling tool, Ansys HFSS. Comparison among the design topologies could be performed in their crosstalk reduction performance for return loss, insertion loss, FEXT and NEXT in frequency domain. With the analysis of performance aspects, advantages and disadvantages of each design topologies, an optimum crosstalk mitigation technique is investigated in microstrip structure for DDR5 signals. Validation is done for the performance in optimum techniques and design topologies.