Publication: Analysis of void formation for no-flow underfill process using numerical simulation and machine learning-based methods
| datacite.subject.fos | oecd::Engineering and technology::Mechanical engineering | |
| dc.contributor.author | Nashrudin, Muhammad Naqib | |
| dc.date.accessioned | 2024-01-22T09:21:31Z | |
| dc.date.available | 2024-01-22T09:21:31Z | |
| dc.date.issued | 2022-09-01 | |
| dc.description.abstract | The no-flow underfill process has been developed as an alternative to the conventional capillary flow underfill. It offers low cost and lead time production effectively due to the integration of simultaneous reflow of solder interconnect and cure of underfill material. Somehow, no-flow underfill also faces the same reliability issue which is the potential void formation during the process. The research on the void formation issue in no-flow underfill has been found scarce. In addition, the research works on no-flow underfill focused on the experimental method which is costly and very limited to study the root cause of the issue. Therefore, this research presents a numerical simulation study of the no-flow underfill which has the ability to track dynamically the movement of the flow of underfill in real time during the process. This research investigates and predicts the possible void formation of no-flow underfill. Three major parameters were selected to align with industry requirements which are chip placement speed, bump pitches and viscosity of underfill. Subsequently, previous literature of no-flow underfill experiment, industrial no-flow underfill experiment and current scaled-up imitated flip-chip experiment were compared in term of flow and void formation percentage to validate with the current numerical simulation. Overall, the current numerical simulation produced low discrepancy which is less than 15% error among all the experiments and affirmed the capability and accuracy of the numerical simulation model. It was found that the void formation rate increases with the chip placement speed but decreases with the increase in bump pitch. The highest chip placement speed of 14 mm/s produces 4-6% meanwhile, the low chip placement speed (2-5 mm/s) produces around 2-3.5% of void formation. Moreover, several supervised machine learning prediction-based methods such as linear regression, decision forest regression and neural network regression were implemented to train the numerical values and to investigate further the most significant parameter that affects the void formation in the chip. It is observed that linear regression, decision forest regression and neural network regression produced mean absolute errors between 0.1588, 0.176375, and 0.1818, respectively. The neural network regression is the preferred algorithm method of machine learning in the study since it shows the least error with a high R2 value of 0.95159. Based on permutation feature importance, the most significant parameter that affect the formation of void in the no-flow underfill was chip placement speed compared to bump pitches and underfill’s viscosity with a score of 1.7916, 0.2962 and 0.000878, respectively. This research provided engineers in the microelectronic industry with a deep understanding of the void formation and expected to provide an appropriate guide to minimize the failure for the development of no-flow underfill in the future. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/18178 | |
| dc.language.iso | en | |
| dc.title | Analysis of void formation for no-flow underfill process using numerical simulation and machine learning-based methods | |
| dc.type | Resource Types::text::thesis | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |