Design And Implementation Of Up-Conversion Mixer And Lc- Quadrature Oscillator For Ieee 802.11 A Wlan Transmitter Application Utilizing 0.18 F.!M Cmos Technology
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Date
2008-11
Authors
Harikrishnan Ramiah
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Abstract
The drive for cost reduction has led to the use of CMOS technology for highly
integrated radios. This work proposes a low voltage, folded, bias point compensation
integrated CMOS active mixer with current draining adaptation to enhance the linearity
and switching efficiency of the transconductor and pMOS based switching quad stage
accommodating 5.15 GHz to 5.35 GHz, IEEE 802.11 a WLAN two step up-conversion
transmitter standards. An enhanced investigation and design of a source injection
parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO) in comparison
of the conventional LC-QVCO realized in pMOS based cross coupled switching stage
is also presented. The design, implementation and characterization of the
complementary stage SIPC LC-QVCO with integrated 50 n cross coupled open drain
buffer, is subsequently proposed adapting the highlighted wireless standard.
Implemented in 0.18 flm, 6 metal, 1 poly, 1.8 V standard CMOS technology and
catering to the need of integration in the proposed up-conversion mixer and SIPCQVCO
topology, a low voltage high precision bandgap reference (BGR) circuit with a
reference voltage simulated at 1.246 V, a regulated resistive weighted bias network
and an integrated depletion mode MOS varactor accommodating a parallel
combination of an on chip self shielding stacked spiral inductor forming an LC tank
resonator, is presented. The compensated bias network integrated up-conversion
mixer topology exhibit a comparable simulated linearity of 12.57 dBm with the
accompanying simulated third order adjacent interferer (lIPJ ) and an input dynamic
range (mdB) of 6.62 dBm at 3.5 GHz of LO frequency, with 10 - 500 MHz of input
baseband frequency. The corresponding standalone up-conversion mixer topology
independently dissipates 5.58 mW of simulated power. Accompanied with bondwire
and parasitic load degradation, the standalone architecture measures an output power
of -65.57 dBm at the up-converted sideband, with -22 dBm and -10 dBm of input
baseband (BB) and local oscillator (LO) power, respectively. The input bias network to
the transconductor stage of the proposed up-conversion mixer observes a simulated
bias voltage, Vb variation of approximately 4 mV over the temperature range of -40°C
to 80°C while dissipating 0.986 mW of simulated power. The complementary and
single coupled pMOS based SIPC LC-QVCO topology indicates a simulated phase
noise performance of -113.22 dBc/Hz and -111.43 dBc/Hz at an offset frequency of 1
MHz, respectively. The respective simulated power dissipation in the complementary
and single coupled pMOS stage is indicated to be 17.73 mWand 15.42 mW with
accompanying 6.5 % and 32.5 % of simulated tuning range at 1.8 V of supply voltage.
The proposed complementary based SIPC-QVCO architecture measures an oscillation
at 2.67 GHz, with a tuning range degradation of 35 %. The integrating LC resonator
tank exhibits, approximately -32 % of simulated independent varactor tuning with
approximately 5.8, tank quality factor Qtank at 3.5 GHz of center frequency. In this work
a voltage precision bandgap reference, ten different independent stacked spiral
inductor, an up-conversion mixer and a complementary SIPC-QVCO architecture were
designed and characterized independently.
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Keywords
The drive for cost reduction has led , technology for highly integrated radios