Low Power Design Techniques And Its Implementation On Direct Memory Access (DMA)
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Date
2012-08
Authors
Shabagran Gandi
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Abstract
As the number of transistors in a SoC has been increasing rapidly, the integration
complexity has increased as well. Besides complexity, IC designers also faced some other
challenges including maintaining the power, performance and area of an IC. Among these
challenges, maintaining power has been an important aspect that needs attention. Instead of
enhancing the packaging quality to preserve power consumption, IC designers practice low
power design techniques for a VLSI design to overcome this issue. There are quite a number of
low power design techniques including, clock gating, power gating, multi-supply voltage and
others. In this thesis, the discussion will be based on the clock gating technique which is
implemented on direct memory access (DMA) for dynamic power reduction. Instead of using
the normal fine-grain clock gating (FGCG), some modifications have been done to the circuit by
utilizing the reset signal as an additional enable pin to trigger the clock and this was proposed as
modified-FGCG (m-FGCG). The modification approach and the method to identify appropriate
clock gating candidates have been also discussed with some illustrations. 38% of dynamic power
reduction has been achieved when m-FGCG is implemented with global clock gating (GCG).
Another technique, channel clock gating (CCG) which is specifically for seven channels in
DMA, has been proposed as well. By default, all the clock signals in each of the channel will
toggle all the time irrespective, it is used or not. Hence, CCG technique has the ability to
overcome this redundant event by gating the clock signals when the channel is not being used. If
none of the channels are requested, the entire clock signal for the DMA controller (DMAC) will
be gated with CCG technique. As m-FGCG technique, this CCG technique is also meant for
dynamic power reduction. A total of 28% of dynamic power reduction is gained by simultaneous
implementation of CCG and GCG techniques.
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Keywords
As the number of transistors in a SoC has been increasing rapidly , the integration complexity has increased as well. Besides complexity,