Design and simulation of low power Comparator using low power design Techniques for analog circuits

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dc.contributor.authorSyafira Rasidi
dc.date.accessioned2021-03-18T03:00:14Z
dc.date.available2021-03-18T03:00:14Z
dc.date.issued2018-06
dc.description.abstractComparator is one of the main blocks that plays an important role in overall performance of analog to digital converters (ADC) in all modern technology devices. High speed devices with low voltage and low power are considered essential for industrial application. Design a low power comparator with high speed is required to accomplish the requirements mostly in electronic devices that necessity for high speed ADCs. However, high speed device that lead the scaling down of CMOS process technology will consumed more power. The power reduction techniques are explored in electronic integrated circuit (IC) design. Power reduction techniques such as Multi Threshold Super Cut-off Stack (MTSCStack), Dual Threshold Transistor Stacking (DTTS), bulk-driven current mirror, NMOS bulk-driven differential pair and PMOS bulk-driven differential pair were studied. The aim of this study is to investigate the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using 0.13µm CMOS process. Proposed comparator (conventional comparator with MTSCStack & DTTS & PMOS bulk-driven differential pair) shows result of 11.1 mV for offset, 19.8 mV for resolution, 40.5 for voltage gain, 21.86 ns for propagation delay, 4.06 µW for static power, 18.91 µW for dynamic power and 22.97 µW for total power.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/12272
dc.language.isoenen_US
dc.titleDesign and simulation of low power Comparator using low power design Techniques for analog circuitsen_US
dc.typeOtheren_US
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