Developing TLV320A1C10 V93V dual sites test solution including digital loop-back test mode
| dc.contributor.author | Mohamad Nizam Bin Othman | |
| dc.date.accessioned | 2021-02-23T03:44:07Z | |
| dc.date.available | 2021-02-23T03:44:07Z | |
| dc.date.issued | 2019-06 | |
| dc.description.abstract | Testing is the final step in manufacturing process especially it used in semiconductor industry that process the integrated circuit (IC). Nowadays, IC is more demanding and it is useful in any application such as computer, vehicle, appliance in industrial and many more. So that, testing the IC is getting complicated and need to do lot of tests on IC to ensure the performance comply into specification and improve product cost. For this project is about on how to test the integrated circuit (IC) in alternative ways to bring benefits to semiconductor industry today. The improved methodology is started studying and understand the datasheet for DUT and then create the test plan as a guideline. It is important because it would make easier to do the test program for this device for testing. In this project, the V93K tester is used to test the DUT after placing on it and V93K software is used as a platform for developing the test program and interface between user and tester for testing the DUT. The additional test is involved in test program is digital loop-back test mode. After all tests are debugged, the result should get all pass in dual sites. The parallel test execution of a 100ms with a 20ms which fails at rate of 20% will effect negatively the production test time and provide that the 20ms was the first to be test in sequence program. In general, the test time of the slowest IP core should be less than 50% of the overall test time. With these results, it is deduced that all tests on DUT will be passed when comparing the actual results from test program with the DUT datasheet. It means the results from test program (simulation) are almost same with the results from DUT datasheet. It can be achieving the improvement by using proposed methodology. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/11470 | |
| dc.language.iso | en | en_US |
| dc.title | Developing TLV320A1C10 V93V dual sites test solution including digital loop-back test mode | en_US |
| dc.type | Other | en_US |
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