An investigation on lector (leakage control transistors) technique
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Date
2019-05
Authors
Muhammad Hanif Bin Ali
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Abstract
Battery power is one of the important criteria to be considered by the users when they want to purchase their own portable devices. In order, to maximise the battery life, the manufacturer need to consider the low power requirement on their designed. There are two types of power consumption in CMOS circuit, there are static and dynamic power consumption. Leakage power consumption is one of the major problem when designing low power CMOS circuit. There are many techniques that can overcome the leakage power consumption issue such as sleep transistor technique, forced stack technique, sleepy stack technique, sleepy keeper technique and LECTOR technique. This project will focused on LECTOR technique. LECTOR (Leakage Control Transistor) is one of the technique that can reduce leakage power consumption in CMOS circuit by reducing the leakage current. In this technique, the CMOS circuit will have two extra leakage control transistors, which are self-controlled, in the path from supply to ground which introduce resistances. The objective of this work is to investigate on the implementation of the leakage control transistor (LECTOR) on NAND gate circuit using 130 nm technology and to make comparison of the LECTOR incorporated CMOS circuits with conventional NAND gate circuit in terms of power consumption. The conventional NAND gate and NAND gate implemented with LECTOR technique will be designed in this project. The static and dynamic power consumption was measured in both circuits and the comparison was made. The static and dynamic power consumption for NAND gate circuits is 162.64 picoWatt and 17.75 microWatt, respectively while for NAND gate with LECTOR technique is 141.67 picoWatt and 13.5 microWatt, respectively. From the results obtained, it show that LECTOR technique can be used in the industry for portable devices manufacturing to improve the battery life for that portable devices.