A 0.13-μm cmos reconfigurable power constrained simultaneous noise and input matching pcsnim low noise amplifier lna for multi-standard 0.9, 1.8 and 2.1 ghz mobile application
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Date
2016-06-01
Authors
Awatif Hashim
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Abstract
The wireless communication industry is experiencing tremendous growth. Previously,
multi-standard receivers were designed using parallel architecture to accommodate
multiple standards. However, for each path, the area consumption is high which
increases cost of fabrication. Responding to the demand for a low-cost and high performance wireless front-end, many intensive researches on CMOS radio-frequency
(RF) front-end circuits have been carried out. This project merges the parallel paths
into a single path wireless receiver. The ultimate goal is to minimize the trade-off
between high performance, smaller size and low-cost at low power consumption design.
The target of this project is to design a multi-standard low noise amplifier
(LNA) for three standards frequency bands. To demonstrate the effectiveness of the
design technique, an LNA design is presented for multi-standard single path LNA
with the switching concept. The design can select operating frequency band by
switching the switches which are adopted at the input and output matching network.
A multi-standard Power Constrained Simultaneous Noise and Input Matching
(PCSNIM) topology was implemented. The multi-standard LNA is operated at 0.9,
1.8 and 2.1 GHz frequencies. The design covers wireless standards of GSM900,
DCS1800 and W-CDMA applications. The design was implemented on 0.13-μm 8-
metal CMOS process. The multi-standard LNA shows the noise figure (NF) as low
as 1.72 dB at 1.8 GHz and 1.85 dB at 2.1 GHz. The gain is in the range 10 up to 11
dB. The third order intercept point (IIP3) is 0.2 dBm (at 1.8 GHz), -1 dBm (at 2.1
GHz) and -2 dBm (at 0.9 GHz) while IP1dB compression point is -12.2 dBm (at 0.9
GHz), -11.5 dBm (at 1.8 GHz) and -11 dBm (at 2.1 GHz). The power consumption
of the design is 7.42 mW with 1.2 V power supply.