Design of 0.13-um CMOS Low Noise Amplifier with Enhanced Input Matching Performance and Flat Gain for Cognitive Radio Application
| dc.contributor.author | Thinnesh Kumar Ramakrishnan | |
| dc.date.accessioned | 2021-03-18T03:18:07Z | |
| dc.date.available | 2021-03-18T03:18:07Z | |
| dc.date.issued | 2018-06 | |
| dc.description.abstract | Ultrawideband (UWB) technology is very effective technology with huge data transmission rates over 3.1-10.6GHz frequency band with minimum utilization of power. Low noise amplifier (LNA) is typically the first stage of a receiver whose performance greatly affects the overall receiver performance. In UWB Cognitive Radio (CR) system, the LNA must satisfy stringent requirements of low noise, high gain, and high linearity, as well as low power consumption over a very wide bandwidth. This thesis presents the design of UWB LNA with resistive feedback and inductive degeneration for the frequency of 300MHZ-10GHz. Focus given on improving the input matching, S11 and optimizing LNA for better performance across the wideband for the respective topology. The effects of passive RF components on LNA were also investigated and discussed in this work. The LNA was designed in Silterra’s 0.13-μm CMOS process technology and the pre-layout simulation were executed using Cadence SpectreRF. The LNA optimization are conducted using Cadence’s parametric analysis. The optimizations were made on the components that are hypothesized to contribute most to the S11 performance and to the overall LNA performance as well. Final steps of this project were on optimizing the LNA with passive RF components for best performance in this topology. This design can achieve gain as high as 17.67 dB, lowest NF of 3.36dB, 𝑆12<-49 dB, S22 <-10 and 𝐾𝑓 > 1 within the desired bandwidth. The S11 of this design achieved value below <-10 dB for 4.2 MHz-10 GHz frequency. This design is able to achieve IIP3 of -10.86 dB while the value of IP1dB is -17.93 dB at 2 GHz in pre-layout simulation. The power consumption of the LNA is 9.6 mW with 1.2V voltage supply. These performances indicate that the design is able to achieve all the objectives set for this project. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/12274 | |
| dc.language.iso | en | en_US |
| dc.title | Design of 0.13-um CMOS Low Noise Amplifier with Enhanced Input Matching Performance and Flat Gain for Cognitive Radio Application | en_US |
| dc.type | Other | en_US |
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