Compact modeling of deep submicron CMOS transistor with shallow trench isolation mechanical stress effect

Compact modeling of deep submicron CMOS transistor with shallow trench isolation mechanical stress effect

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dc.contributor.author	Tan, Philip Beow Yew
dc.date.accessioned	2016-11-16T01:48:40Z
dc.date.available	2016-11-16T01:48:40Z
dc.date.issued	2008-08
dc.description.abstract	This thesis introduces a compact model, two empirical-based models and a physical-based model of Shallow Trench Isolation (STI) mechanical stress effect on deep submicron CMOS transistor. The compact STI x-stress model is used to capture the stress effect in the channel length direction. This model is simpler than the BSIM4 STI stress model, but able to achieve the similar accuracy. Two new characteristics of STI x-stress have been identified. The first characteristic is the fact that the STI xstress effect on CMOS transistor varies for different transistor channel widths. An empirical width dependence of STI x-stress effect model has been proposed to capture this effect. The second new characteristic is the fact that STI x-stress effect changes the CMOS transistor mismatch characteristics. An empirical Monte Carlo model is proposed to capture this effect. A new hook shaped saturation drain current, Idsat curve versus channel width has been identified. This curve cannot be modeled using the BSIM4 STI stress model. By using a new layout method, the physical characteristics of the curve are identified. The hook shaped Idsat curve is caused by the combined effects of STI y-stress (stress in the channel width direction) that degrades the Idsat and the Delta Width (OW) effect that increases the Idsat• Based on the physical characteristics, a new physical-based STI y-stress model is proposed to capture the hook shaped Idsat behavior. The accuracy of the models in this thesis is verified on actual silicon data fabricated using Silterra's industry-standard 0.18 I-lm and 0.13 I-lm CMOS technologies. These new models are incorporated into the BSIM3v3 model by using macro model method (also known as subcircuit method). The two SPICE parameters, the zero back bias threshold voltage parameter, PvthO and the carrier mobility parameter, Puo, are used for developing these models. The difference in simulation time between the macro model and the conventional model is insignificant « 5 %).	en_US
dc.identifier.uri	http://hdl.handle.net/123456789/3094
dc.subject	The compact STI x-stress model is used to capture	en_US
dc.subject	the stress effect in the channel length direction.	en_US
dc.title	Compact modeling of deep submicron CMOS transistor with shallow trench isolation mechanical stress effect	en_US
dc.type	Thesis	en_US

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