Design and analysis of a cmos image sensor
| dc.contributor.author | Nuranisah Halim | |
| dc.date.accessioned | 2021-03-18T02:40:56Z | |
| dc.date.available | 2021-03-18T02:40:56Z | |
| dc.date.issued | 2018-06 | |
| dc.description.abstract | This project presents a chip designed for the purpose of evaluating the design method in implementing a CMOS Image Sensor Technology (CIS) for Active Pixel Sensor (APS) based vision applications. For this purpose, the possible ways of implementing pixel array sensors and readout related circuit with standard CMOS technology using commercially available 0.18 μm CMOS processes with both p-well and n-well implementations were explored. This is to ensure that our image sensors applicable for many applications. Towards this aim, this research CIS technology have to improve its characteristics such as sensitivity, dark current and noise that are strongly layout dependent. This chip includes a set of pixel architectures where different parameters have been modified, layout of active diffusion and threshold voltage of the source follower transistor. This CMOS imager only has 1 pixel, but that can be improved by changing the scan logic because the size of this pixel array is a metric that gives an indication of the performance image sensor where it is expressed as a megapixel. There are many ways to implement CMOS pixel sensing using accumulation mode. The simplest active pixel sensing implementation is 3T-APS is implemented in this project. The voltage swing obtained from 1 pixel of this 3T-APS is 2.66V. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/12268 | |
| dc.language.iso | en | en_US |
| dc.title | Design and analysis of a cmos image sensor | en_US |
| dc.type | Other | en_US |
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