Clock Gating Technique For Power Reduction In Digital Design
| dc.contributor.author | Khor, Peng Lim | |
| dc.date.accessioned | 2019-06-24T02:15:14Z | |
| dc.date.available | 2019-06-24T02:15:14Z | |
| dc.date.issued | 2012-12 | |
| dc.description.abstract | Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not give the same power saving efficiency when the operating frequency increases. Power reduction effectiveness decreases follows downward of the design flow. For an IC design house without fabrication factory, levels of power optimization in the design flow are very limited. In this research, selected power reduction techniques are used with different operating frequency to investigate the effectiveness of the techniques in a high speed design. This research focused on the clock-gating power convergence technique to bring the power optimization benefit for the IC design houses that without fabrication factory. With the same power reduction technique, different implementation of the technique will give different efficiency. This research included different approach of clock-gating in a few scenarios to investigate the real world situation. Process technology plays the important role in selecting power convergence techniques to be implemented. With advance process technology below 90nm scale, the leakage power consumption becomes dominant. Hence, adding additional logic to reduce dynamic power consumption might give worse result. This research included few technology libraries which are 32nm, 90nm, 350nm and 500nm for comparison. The result shows that clock-gating technique is very efficient at high speed operating frequency but the benefit decreases when running in low operating frequency. New process technologies also shows that clock-gating technique is not so efficient due to the transistor device is leakage power dominant while clock-gating is focusing on reducing dynamic power consumption. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/8347 | |
| dc.language.iso | en | en_US |
| dc.publisher | Universiti Sains Malaysia | en_US |
| dc.subject | Multiple power reduction techniques are used to keep | en_US |
| dc.subject | power consumption under control even when the operating frequency is high | en_US |
| dc.title | Clock Gating Technique For Power Reduction In Digital Design | en_US |
| dc.type | Thesis | en_US |
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