Study Of The Relationship Between Delta Delay And Adjacent Parallel Wire Length In 45 Nanometer Process Technology

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dc.contributor.authorMohamed, Shamsul Anuar
dc.date.accessioned2019-11-18T06:50:54Z
dc.date.available2019-11-18T06:50:54Z
dc.date.issued2014-01
dc.description.abstractHierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL), synthesis, place and route, timing closure and various other analyses before sign-off. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key issue for Deep Sub-Micron design. Post silicon bug due to noise and signal integrity can be prevented and fixed at early stage of the IC design cycle. The purpose of this research is to establish a preventive measurement for adjacent wire that can travel in parallel for 45nm technology. The intention is to ensure that a complex design can be delivered to the market with accurate, fast and trusted analysis and provide sign-off solution. Main approach is to conduct the relationship study between delta delay and adjacent parallel wire in 45 nanometer (nm) process technology and provide a preventive measurement to limit the adjacent wire can travel in parallel. The design is explored thoroughly to study the relationship between delay noise and adjacent parallel wire. The correlation is translated into an equation to estimate the delay noise produced with a certain length of adjacent parallel wire.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/9197
dc.language.isoenen_US
dc.publisherUniversiti Sains Malaysiaen_US
dc.subjectDelta Delay And Adjacent Parallel Wireen_US
dc.subject45 Nanometer Processen_US
dc.titleStudy Of The Relationship Between Delta Delay And Adjacent Parallel Wire Length In 45 Nanometer Process Technologyen_US
dc.typeThesisen_US
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