Design and simulation of low power comparator using dtts and mtscstack technques
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Date
2015-08-01
Authors
Pragash Mayar Krishnan
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Abstract
The demand for high speed and low power comparator in Analog to Digital converter
(ADC) is growing rapidly. Comparator is an important building block in ADC. Power
consumption tends to be a major concern in today’s technology especially the electronic
devices that are operating at high speed with multi functionality. Thus, the need is
increasing for low power electronic devices without compromising its performance. In
this study, conventional comparator, comparator with reduced VDD, comparator with
MTSCStack (Multi Threshold Super Cut of Stack) and comparator with DTTS (Dual
Threshold Transistor Stacking) have been designed and simulated in 0.13 μm CMOS
process technology. Then, based on the study a low power comparator is proposed with
MTSCStack and DTTS techniques. MTSCStack is proposed in order to decrease the
leakage power in active mode and retaining the logic state of the comparator during the
idle state. In other hand, DTSS is proposed to decrease the leakage current with less
impact on the delay. In addition, the total power consumption especially dynamic power
has been reduced by large amount by decreasing the VDD of the comparator. The static
power and dynamic power of the post-layout proposed comparator is 797 pW and 17.55
μW respectively.