A systematical approach for a robust electrostatic discharge (esd) design
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Date
2016-05-01
Authors
Chuah ; Cheow Theng
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Abstract
With the increase events of ESD-induced chip failure, it has become vital for the IC
design community to develop a comprehensive ESD design flow with various automated tools that can efficiently detect ESD design weakness early in the design phase. We need to get the design (ESD design in this context) right at the very first time. Existing ESD design verification flow is either layout dependent (layout design rule checker), circuit dependent (circuit simulation) or too late to intercept the ESD design problem. A proposed ESD design flow is demonstrated with some correct-by-construction ESD design idea. An ESD design methodology and protection strategy for digital systems, robust to ESD events, is developed and validated for commercial 45nm, 65 nm and 90 nm MOS technologies. The ESD design flow basically takes care of the HBM, MM and CDM ESD stress models. The ESD design flow demonstrates different type of design errors that the tools have uncovered
and justify the need for this enhanced ESD protection strategy. We have layout design rule checker, circuit simulation, auto clamp placement tool and other tools in our ESD design flow. Using these measurement, modeling and simulation techniques, the design methodology and protection strategy was successfully implemented into a commercial mainstream design flow. Specific IC test chips, designed using conventional ESD rules targeted for ESD stress protection, were used as test vehicles for the new methodology; resulting design changes resulted in chips that passed levels of ESD stress ( industrial standard of HBM 2.5kV, MM 200V and CDM 500V) with virtually no major design amendments.