Thermal resistance in electronic packaging
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Date
2002-04
Authors
Lim Fong
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Abstract
Almost 55% of failure in electronic packages occur due to thermal problems. Junction
temperature, Tj, is the highest temperature of the operating portion of a semiconductor
device. Since the heat conduction is the only mode of heat transfer within the package,
it is essential to determine the thermal resistance between the die and the outer surface.
Both two-dimensional and three-dimensional effects exist within the package, and this
can be taken into account using the conduction shape factor, S. Once conduction shape
factor is known, the thermal resistance for the heat flow can be calculated. Tj is derived
from the value of the thermal resistance obtained. Several new conduction shape factors
are developed for shapes encountered in an electronic package. Shape factor is then
used to predict the Tj for a Microleadframe (MLF) package. The predicted value is
found to be in good agreement with the result of FEM simulation.
Electronic engineer uses a compact model to predict the heat flow inside a
package. A compact model is a simplification of a full thermal model of an electronic
package. Several methodologies of deriving a compact model are investigated and the
best methodology is used to derive a compact model for selected electronic packages,
namely Shrink Small Outline (SSOP) and MLF packages. The results compared well to
the compact model derived using Genetic Algorithm method. For SSOP, the final
derived compact model is a better network in terms of accuracy compared to the
network available, suggested by Vinke and Lasance (1997). For MLF, a new compact
model is derived. Both derived compact models are able to predict the Tj of the
packages in a new environment with 97% accuracy.
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Keywords
Almost 55% of failure in electronic packages , occur due to thermal problems