Design of 0.13-ยตm cmos LNA with flat gain for cognitive radio application
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Date
2017-06
Authors
Faris Amsyar Bin Ahmad Zhaki
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Abstract
A low noise amplifier (LNA) is one of the important component in a CR receiver that amplifies a very low-power signal and minimized additional noise from the received signal. The biggest challenge in designing an LNA for ultra-wideband (UWB) application as required in CR, is to obtain high flat gain throughout wide bandwidth. This thesis presents the design of CMOS LNA with high flat gain for ultra-wideband (UWB) application between 300 MHz to 10 GHz frequency spectrum. In order to implement the LNA in CR application, the LNA must be able to provide wide bandwidth operation at high flat gain. Besides focusing on the targeted high flat gain throughout the wide bandwidth, other performance metrics must be optimized to fulfill the design target specification. The proposed LNA design is a cascode amplifier with resistive shunt feedback, determined based on its merits that can fulfill the design requirement of this work. The LNA was designed in Silterraโs 0.13-ยตm CMOS process technology and the pre-layout simulation was executed by using Cadence SpectreRF. The achieved gain is within 18.56 dB to 21.31 dB with a variation of 2.75 ๐๐ต (๐.๐. 15%). The noise figure (NF) is between 4.41 dB โ 5 dB, ๐12 < -49.43 and ๐พ๐ > 1 were achieved within the operating bandwidth. This design is able to achieve IIP3 value of -7.97 dB while the value of IP1dB is -18.4377 dB at 4 GHz in pre-layout simulation. The power consumption is 34.8 mW at 1.2V. The performances indicated that the design is able to achieved all the set objective.