A 0.8 – 2.4 Gbps Driver With Adjustable De-Emphasis Scheme For Ddr3 Memory Interface
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Date
2014-01
Authors
Lim, Zong Zheng
Journal Title
Journal ISSN
Volume Title
Publisher
Universiti Sains Malaysia
Abstract
The need for greater memory bandwidth to boost the computer system
performance has driven system memory evolution to Double Data Rate Synchronous
Dynamic Read Access Memory (DDR SDRAM) technologies. Trends to maximize
memory bandwidth have caused Inter-Symbol Interference (ISI) become significant
which degraded the signal integrity of transmitted data. In this research, a driver
architecture with adjustable de-emphasis and impedance control scheme is proposed for
high-data rate and high-density DDR3 SDRAM memory system. The proposed driver is
implemented using 45 nm CMOS process technology. The designs and implementations
of the proposed driver involve the design of driver architecture, data controller,
impedance calibration block with reference generator as well as the layout for critical
analog circuits i.e. three driver segments for post-layout simulations to ensure the
parasitic in layout does not has significant effect on driver performances. The driver has
15 de-emphasis legs that can form 15 de-emphasis voltage levels that capable of
reducing ISI-induced jitter at high operating frequency. Moreover, high density DDR3
memory system can deteriorate the far-end eye jitter and eye height that causes
difficulties in data sampling and recovery. Thus, the driving impedance of the proposed
driver can be programmed between 20, 30 and 40 Ω to compensate the variability of
board routing effect in memory system and hence, improving signal integrity.
Description
Keywords
0.8 – 2.4 Gbps Driver , Ddr3 Memory