Rekabentuk Penuras Digit Fir Termusnah Untuk Aplikasi Sonar Menggunakan Teknologi FPGA
| dc.contributor.author | MOhd Zain, Dalmataksiah | |
| dc.date.accessioned | 2016-10-17T07:02:11Z | |
| dc.date.available | 2016-10-17T07:02:11Z | |
| dc.date.issued | 2005-03 | |
| dc.description.abstract | Field Programmable Gate Arrays (FPGA) have become viables alternatives to implementation of high speed semiconductor technology. It is used in many application such as in digital signal processing (DSP). The FPGA current device such as XILINX have power and capacity to implement a FIR filter with high performance and specifICation. In this thesis, the Digital Decimation FIR Low Pass Filter with Linear Phase for Low Frequency (DDFIR) application has been designed to perform the specifications of the sonar system applications. The Remez Exchange Algorithm is used to determine the filter order and to calculate the filter coefficient by using the very simple MATLAB script. The modified direct form structure for linear phase filter hardware realizes this filter with multiplier-free and minimum number of delays and adders. The hardware implementation has been made in Schematic Capture to realize it in FPGA. The hardware simulation is introduced and its performance is verified by investigated the structural timing simulation which is available in the XILINX FOUNDATION 2.1i Tools. The result of simulation shows this filter system achieveds the maximum frequency up to 19.92 MHz. This filter will be downloaded into a FPGA XILINX XC4013XLA. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/2757 | |
| dc.subject | Field Programmable Gate Arrays | en_US |
| dc.subject | implementation of high speed semiconductor technology. | en_US |
| dc.title | Rekabentuk Penuras Digit Fir Termusnah Untuk Aplikasi Sonar Menggunakan Teknologi FPGA | en_US |
| dc.type | Thesis | en_US |
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