Electrostatic discharge protection circuit design in deep sub-micron technology for automotive application
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Date
2018-06-01
Authors
Ng Yit Ming
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Abstract
Many modern semiconductor products are susceptible to the damage of electrostatic discharge (ESD) and this make ESD protection a must for integrated circuits. However, current ESD specifications cause a bottleneck for ESD qualifications especially for the automotive industry segment, which requires more stringent qualification requirements than other applications. The advancement of complementary metal-oxide-semiconductor (CMOS) transistors scaling into the nano-metric regime makes ICs more vulnerable to ESD failures and the implementation of an effective ESD protection designs become very difficult. This research aims to develop a robust ESD protection solution through circuit performance co-design methodologies. Two real test cases of ESD improvements have been studied in detail. This research has shown that the low voltage differential signaling (LVDS) ESD issue can be resolved by optimizing both the high-speed driver gate length and the ESD MOS design. In addition, it is also demonstrated that the fragile ESD robustness in small power domain can be enhanced by introducing a novel ESD clamp. By implementing these ESD improvements, the automotive ESD stringent requirements for both the 2000V human body model (HBM) and the 200V machine model (MM) could be met and enabled the continuation of CMOS scaling.