Design Of Configurable Output Driver For 0.4 – 8.0 Gbps Application

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dc.contributor.authorCh’ng, Siew Sin
dc.date.accessioned2019-12-03T07:18:10Z
dc.date.available2019-12-03T07:18:10Z
dc.date.issued2014-01
dc.description.abstractThis research proposes a configurable output driver that can be configured between two single-ended voltage-mode drivers, a differential voltage-mode driver and a differential current-mode driver to address electronic signaling mismatches between integrated circuits for 0.4 – 8.0 Gbps applications. In addition, four control schemes, namely impedance, output swing, slew rate and de-emphasis control scheme are integrated into configurable output driver to improve signal integrity by addressing the ISI, output switching noise, reflections and output swing deviation. In this research, the designs and implementations of the proposed configurable output driver are developed in four parts. First part includes the design of configurable output driver architecture. Second part is equipping the configurable output driver with driver controller and multileg structure for output impedance and output swing calibration. Third part involves calibration block designs to calibrate output impedance and output swing across PVT (Process, Voltage and Temperature) variations. Last part involves the layout implementation of configurable output driver for post-layout simulations. Besides, through impedance control scheme, output impedance is calibrated at 50 Ω for data transmission and 50, 75 or 150 Ω receive ODT (On-Die Termination) for data reception, with maximum impedance error at ± 5%.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/9260
dc.language.isoenen_US
dc.publisherUniversiti Sains Malaysiaen_US
dc.subjectOutput Driveren_US
dc.subject0.4 – 8.0 Gbps Applicationen_US
dc.titleDesign Of Configurable Output Driver For 0.4 – 8.0 Gbps Applicationen_US
dc.typeThesisen_US
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