FPGA Design Of A Banyan Network Multistage Interconnection Atm Switch Fabric Using Fifo Buffering Technique
Loading...
Date
2001-12
Authors
Abdoulie Barrow
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
Since the early eighties there have been steady and progressive development advances
taking place in the field of communication technology. Tremendous efforts have been
dedicated towards improving network capabilities in a bid to handle the ever increasing
volumes of data traffic, a direct result of increasing data networks integration. The areas
of technology that play prominence in these advances, among others, include ISDN
(Integrated Services Digital Network), B-ISDN (Broadband ISDN), and most
importantly ATM (Asynchronous Transfer Mode). A TM is widely accepted as a
candidate that can provide variety of network capabilities such as efficient traffic
management and handling, besides offering cost-effective and scalable features when it
is implemented in large switching network environment. In such environment
bandwidth requirement also becomes crucial considering the volume of data to transfer.
Hence in all ATM switch designs and implementations it is most essential to aim at
achieving data transfer rates within the Gigabitls or in some cases even Terabitls ranges.
The main concern of this project is to design a single FPGA (Field Programmable Gate
Array) chip-based multi-stage interconnection (MIN) ATM switch fabric based on
Banyan (Delta) topology that can provicie multi-path capability and a data transfer rate
within the Gigabitls range. The design also inch.ides the use of a dual-port RAM FIFO
(First-in-first-out) as an input qu~uing system capab1e of carrying out simultaneous
'read' and 'write' operations. A schematic approach is adopted to build the entire switch
fabric using the XlLlNX Foundation F2.1i software.
The design is completely and successfully translated, mapped, routed and placed on a
single 84-pin FPGA, XIL1NX XC401O-XL. The implementation reports generated
during the timing simulation process indicate that the designed switch fabric can switch
data at rates in the Gigabitls range. The bit stream file generated during the bit
configuration process is loaded onto a physical chip, which is then tested by injecting
test data signals into the defined inputs through a PC parallel port. The outputs are
subsequently observed for the corresponding data signals using a logic analyzer.
Description
Keywords
Asynchronous Transfer Mode , Provide variety of network capabilities