Analysis of partial binary tree network (pbtn) for dynamic element matching (dem) digital to analog converter (dac)
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Date
2016-03-01
Authors
Lim Ee Wey
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Abstract
In many digital systems, high performance DACs is essential to ensure proper
operations. Matched components are required in order to achieve proper data
conversion. Many factors such as process variation and temperature can cause
components to be mismatched therefore it is impossible to fabricate perfectly
matched components all the time. Mismatched components will lead to difference in
designed values and actual values. One of the techniques to reduce the effect of
mismatched components is to use Dynamic Element Matching (DEM) network to
randomize the digital input codes to a DAC. This randomization can help to make
the time averages of the equivalent components at each position to be nearly equal.
The problem with existing DEM implementations is the linearity performance of the
DAC is not as ideal and has glitches due to transitions of multiple switches at the
same time. In this research, the implementation of 2 MSB randomization is proposed
on a Partial Binary Tree Network (PBTN) DEM for a current-steering DAC and its
performance evaluated in terms of glitches, DNL and INL. Comparison was done
for 4-bit BTN, 4-bit PBTN and 4-bit (2 MSB) PBTN. Another comparison was done
for performance for 6-bit & 8-bit (1 MSB) PBTN and 6-bit & 8-bit (2 MSB) PBTN
DEM DAC. Simulation was done and the 8-bit (2 MSB) PBTN DEM DAC yields
maximum glitch of 259.4 mV, DNL of 2.46 LSBs, and DNL of 31.00 LSBs.