Fabrication of gold nanodot on silicon substrate by scanning probe microscopy and its characterization
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Date
2016-02-01
Authors
Teguh Darsono
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Abstract
The application of SPM-based techniques as a fabrication and characterization tool was studied. AFM non-contact mode that operated at room temperature and under vacuum conditions was used to deposit gold nano dots on silicon substrate. This is achieved by controlling the tip–sample distance, using a feedback control system by the application of an external electrostatic force. Application of a voltage pulse of either positive or negative polarity to a 70 nm gold-coated cantilever tip leads to the deposition of gold nanodot. The dimensions of the fabricated gold nanodots are 42.5 – 150.4 nm in diameter, and 2.3 – 7.8 nm in height. It was found there is a tendency that the gold nanodot diameter increases with increasing the voltage pulse. Meanwhile, the height of the gold nanodot increases with increasing of voltage pulse duration. An arbitrary combination of applied voltage pulse amplitude and tip sample distance does not lead to deposition. Dependence on the tip sample distance indicating their dependence on the electric field parameters that control the deposition process and it is found that the electric field threshold field of around 8V/nm. The study of the electrical properties of gold nanodot on silicon substrate were performed using a conductive AFM and shows that the I-V characteristic of these structure acts as a Schottky barrier diode. Current-voltage characteristics of these diodes have been analyzed on the basis of thermionic emission theory. The basic diode parameters such as ideality factor (n) and barrier height (𝜙𝐵) were extracted. The series resistance (RS) values were calculated using Cheung and Cheung’s methods. The diameter-dependent current voltage (I-V) characteristics of gold nanodot on n-type silicon substrate in the diameter range of 50-98 nm have been investigated. The calculated barrier height (𝜙𝐵) for gold nanodot on n-type silicon substrate have varied from 0.56 to 0.74 V, the ideality factor (n) from 3.6 to 1.6, and the series resistance (RS) from 1.22 to 2.85 k. It observed that the ideality factor (n) decreases while the barrier height (𝜙𝐵) increases with increase of diameter. Meanwhile, the series resistance (RS) value decreased with increasing diameter of the diode. Dimensional dependences of the barrier height and ideality factor of Schottky diode are determined by the change of the contribution of peripheral current in Schottky diode with the diameter contact increasing, and the increasing in diameter reduces the contribution of a peripheral current which causes an increase in the barrier height (𝜙𝐵) and a reduction of the ideality factor (n). The temperature-dependent electrical properties of gold nanodot on n-type silicon substrate have been investigated in the wide range temperature of 200 – 300 K. The calculated barrier height (𝜙𝐵) for gold nanodot on n-type silicon substrate have varied from 0.46 to 0.62 V, the ideality factor (n) from 4.3 to 1.2, and the series resistance (RS) from 3.76 to 1.92 k. It is evident that the ideality factor (n), increases with decreasing temperature, while the barrier height (𝜙𝐵) increases with increasing temperature, and the series resistance values (RS) decreases with increasing temperature. The increase of series resistance (Rs) with decreasing of temperature is believed to be due to factors responsible for increase in ideality factor (n) and lack of free carrier concentration at low temperature.