Design and implementation of low power and high performance 4 bit carry lookahead full adder using finfet technology
Loading...
Date
2015-08-01
Authors
Lim Nguk Jie
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
An Arithmetic Logic Unit (ALU) is a digital circuit and used to perform all arithmetic operations and logic operations. Addition is the most important part among of the ALU since it has been used in other arithmetic operation. Now there are three main performance parameters i.e. area, speed and power are focused by VLSI designer to optimize their design. Therefore, improving the speed of addition increase the performance of all other arithmetic operations. The Carry Look-Ahead Adder (CLA) has been chosen because it speeds up the carry computation by reducing the amount of time to determine carry bits. The 4-bit CLA Full Adder can be implemented with different types of transistor, such as FinFET and Metal Oxide Semiconductor Field-Effect Transistor (MOSFET), which may have difference performance in supply voltage variation. In this project, the analysis of the simulated results confirm the feasibility of the 14nm FinFET techniques in Transmission Gate (TG) style full adder design and shows that there is reduction of approximately 52% in the value of power dissipation parameter as compared to CMOS 22nm technique. In conclusion, it has been shown that the proposed CLA circuit in 14nm FinFET in TG provides better speed with the least power dissipation compared to the previous works.