Low power design techniques for analog circuit
| dc.contributor.author | Faez Hazwan Bin Zainudin | |
| dc.date.accessioned | 2021-04-22T01:37:37Z | |
| dc.date.available | 2021-04-22T01:37:37Z | |
| dc.date.issued | 2017-06 | |
| dc.description.abstract | Analog comparator is a circuit that compares two analog signal and produce a digital output from the comparison. Low power consumption and high speed comparator is very important to exchange the analog signal to digital signal at the same time can operate in low power. Use of low power circuit is such a demand for electronic devices even more for electronic devices use batteries to operate. So, designing of low power consumption and high speed comparator become an attention without affecting the performance. In this study, the conventional comparator, comparator with MTSCStack & DTTS, and comparator with bulkdriven has been designed and simulated using Silterra Cadence technology software using 0.13 µm CMOS process. The aim of this study is to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance. The function of MTSCStack technique is to reduce leakage current in active mode and at the same time retain the original state. While, DTTS is reduce leakage current without affecting the performance of the circuit and bulk-driven technique is be able to remove the need of VTH from the signal path when the input signal is applied to bulk. Under this condition, the voltage drop across is required across input and output terminals of the drive. Proposed comparator shows result of 13.6mV for offset, 25.8mV for resolution, 19.3 for voltage gain, 3.46ns for propagation delay, 7.71µW for static power and 16.44 µW for dynamic power. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/13028 | |
| dc.language.iso | en | en_US |
| dc.title | Low power design techniques for analog circuit | en_US |
| dc.type | Other | en_US |
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