High Speed CMOS VCO For Advanced Communications
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Date
2003-10
Authors
Rajagopal, Chakaravarty
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Abstract
The fast growing demand of wireless communications for voice and data has
driven recent efforts to dramatically increase the level of integration in RF transceivers.
One approach to this challenge is to implement all the RF functions in the low-cost
CMOS technology, so that RF and baseband sections can be combined in a single chip.
This in tum dictates an integrated CMOS implementation of the local oscillators with
the same or even better frequency, phase noise and jitter performance than its discrete
counterpart, generally a difficult task using conventional approaches with the available
low-Q integrated inductors.
In this thesis, a 16-bit digitally controlled CMOS voltage controlled oscillator
CDVCO) is described. Here, the fundamental performance limit of a local oscillator
design using negative skewed delay scheme, dual delay path scheme and control word
register scheme with differential delay cell as base is investigated. The distinctive
frequency operation pattern based on the source-coupled differential CMOS delay cell
implementation is analyzed. The result suggests that operating frequency, can be
controlled by varying the delay of differential delay cells.
To demonstrate the proposed concept, some prototypes of this DVCO
implemented in MOSIS HPO.5J.l CMOS process were fabricated. Experimental results
of a 16 Bit CWR controlled 5-stage DVCO achieved controllable frequency range of 1.4
- 2.1 qHz with a linear/quasi-linear range of around 1.7 GHz. This CMOS DVCO
design provides improved frequency stability under thermal fluctuations. Monotone
frequency gain (frequency vs control-word transfer function) with fine stepping (tuning)
in several MHz was verified. This augurs the prospect of accurate frequency lock in a
CMOS all digital PLL (ADPLL) application in digital VLSI communication systems.
Worst ca~e jitter due to digital control transitions at pathological control-word
boundaries for the CMOS DVCO was observed to be less than 80 ps, which is lower
than most of the previously proposed VCOs. Simulation on this oscillator also achieves
-102 dBclHz phase noise at 10KHz offset from carrier frequency of 1 GHz while
dissipating 150 mW from a 3.3 Volt supply.
Description
Keywords
To dramatically increase the level , of integration in RF transceivers