Publication: Pipeline microcontroller synthesizable design
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| dc.contributor.author | Zulkipli, Mohamad Izat Amir | |
| dc.date.accessioned | 2024-09-05T07:35:19Z | |
| dc.date.available | 2024-09-05T07:35:19Z | |
| dc.date.issued | 2009-04-01 | |
| dc.description.abstract | The objective of this project is to design and synthesize a pipeline microcontroller by using MentorGraphic EDA tool software such as Design Architect-IC, Modelsim and Leonardo Spectrum. Pipeline microcontroller is the microcontroller that provides parallel processing sequential order by using 3-stage pipeline design which separated into predecode stage, decode stage and execute stage. This microcontroller synthesizable design exposes the basic environment of how to studies and understanding the related VHDL codes with more further besides understanding more about behavior of the microcontroller and their functionality. The result and experiment has been conduct to the simulation results, schematic, and layout of the pipeline microcontroller. By mastering learning the synthesizable of 3-stage pipeline microcontroller, this project can proceed for the hardware design microcontroller. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/20391 | |
| dc.language.iso | en | |
| dc.title | Pipeline microcontroller synthesizable design | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |