Publication: 1.5-Bit stage analogue-to-digital converter (adc)
No Thumbnail Available
Date
2023-08-01
Authors
Ch’ng, Ooi Keat
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
This report presents the design of 1.5-bit stage Analogue-to-Digital Converter (ADC). In this project, with some assumption considered, the minimum open-loop DC gain, AOL required for this project is calculated as 40dB. Meanwhile, the minimum unity gain frequency, fu of the OTA must be at least 16.0MHz as the ADC designed in this project will be clocked at 8MHz. Average power consumption of the main OTA is expected to be less than 40mW. Silterra 180nm process technology is used in this work. The architecture of 1.5-bit stage ADC mainly consists of an operational transconductance amplifier (OTA) as the core element. Generally, the 1.5-bit stage is made up of a 2-bit comparator, a digital logic circuit and a residue amplifier. The main function of the comparators is to emonstrate that an input signal is either larger or less than a predetermined reference voltage. The digital logic circuit serves as switches to allow the residue amplifier to function by receiving a 2-bit digital input from the comparator. Based on the results obtained, the main OTA in this project has specifications such that 45.0dB for the open-loop DC gain, 470.11MHz for unity-gain frequency, 79.52° for phase margin, and 27.117mW for average power consumption for the main OTA. In short, all the specifications for this main OTA have all achieved the minimum requirement of the main OTA design. The three blocks for the overall design of 1.5-bit stage ADC, which are the 2-bit comparator, digital logic circuit, and lastly the residue amplifier, are all carried out their specific. functions successfully as all of them are verified throughout the testbench simulations with the desired outcomes.