Publication: Design of ring oscillator with trimming circuit for performance tuning in CMOS 180nm technology
Date
2024-07
Authors
Lai, Yong Juin
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Abstract
Ring oscillator is an important component that used in many electronic circuits as it is able to generate clock frequency for the circuit. The output frequency that generated by the ring oscillator needs to be consistent when the ring oscillator undergo the process, voltage and temperature (PVT) variations. However, the performance of the ring oscillator is affected when undergo the process, voltage and temperature variations as the variations happen is sensitive to the ring oscillator. It will cause the frequency shifting happens in the output of the ring oscillator and degrades its clocking performance. Furthermore, the process variation will provoke uncertainty, voltage variations will cause the deviation in frequency from the ideal operating conditions and the temperature variations will cause the frequency instability. Hence, the trimming circuit is required to tune back the frequency when under PVT variations. A ring oscillator with trimming circuit for performance tuning is designed in this project. This project is constructed by using CMOS 180nm Technology and the Cadence Virtuoso Software is used to design and perform simulation for the designed circuit. An output frequency of 700MHz that obtained from ring oscillator is expected from the results of this project under Process, Variation and Temperature (PVT) variations. In the schematic design of overall circuit, there are 3 sets of capacitors are placed within the ring oscillator, each capacitor is connected to 1 nMOS switch, and each set of capacitors is connected to 1 voltage source. The capacitor and the nMOS switch in the same set have the same properties. Since there are total 3 voltage sources, Vtune1, Vtune2 and Vtune3 are used to control the ON of OFF of each set of
capacitors, hence there are total of 8 arrangements of bits used for frequency correction. The simulations are then carried out for all the PVT cases. The arrangements of bits that selected for all cases in the pre- and post-layout simulation are different as the desired frequency is not obtained with the original arrangement of bits that selected in pre-layout simulation. The simulation results of frequency for all PVT cases in post-layout simulation are from 600MHz
to 800MHz, all cases have an arrangement of bits able to obtain the desired frequency, 700MHz. The power consumption in pre-layout simulation is 33.1457µW, and in the post-layout simulation is 29.3857µW.