Publication: Reduced-component multilevel inverter with asymmetrical source configuration
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Date
2024-07
Authors
Loi, Zong Ye
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Abstract
Multilevel inverters play a vital role in power systems by converting direct current into usable alternating current. They facilitate the integration of renewable
energy sources into high-power applications, offering enhanced power quality, mitigating insulation faults and prolonging load lifespan by minimizing voltage spikes. As technology advances, the trend in multilevel topology is to maximize output levels so that the generated waveform closely resembles a pure sinusoidal waveform. However, the two main categories of multilevel inverters, isolated and non-isolated, face challenges in achieving a high number of output levels, the non-isolated inverter employs a comprehensive floating capacitor, whereas the isolated inverter requires extensive power switches, which increase marginally with the number of output levels. The capacitors are the most voluminous and heaviest parts in inverter, causing the non isolated inverter to become bulky and heavy. Meanwhile, the extensive power switches used in isolated inverters incur higher costs than capacitors. These factors underscore the trade-offs between size, weight and cost in the design and implementation of multilevel inverters. Therefore, this thesis aims to address these two main issues by
exploring a strategic way to balance between the number of output levels and the reduced number of components. Specifically, an asymmetrical source configuration of multilevel topologies with reduced components has been proposed to output a relatively high number of 49 output levels. Detailed design parameters and the switching state of the proposed multilevel inverter are discussed. The validation of the proposed multilevel inverter is conducted using MATLAB Simulink and the performance of the multilevel inverter is evaluated based on the number of components used, power sharing among the sources, TSV and THD. In summary, the voltage and current THD under resistive loads recorded a percentage of 1.65%, while the current THD depends on the value of inductor under the RL load test. The individual harmonics of the output current are also tested to be within the specified TEC/EN 61000-3-2 standard. The number of components used in the proposed topology is less and the TSV is reasonable while compared to other existing topologies.