Design of fpga address register in 28nm process technology based on standard cell based approach
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Date
2013-07-01
Authors
Choo , Chew Ming
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Abstract
Traditionally, Field Programmable Gate Array (FPGA) Address Register (AR) is
designed using full custom approach. With geometries shrink on advance process
node, there is a need to reconsider the design approach used to design FPGA AR
because of increased design cycle and complexity that lead to more iteration time on
closing block timing. Significant design effort and challenges are required in 28nm
and beyond when using full custom approach. Therefore, standard cell based
approach is used to design the FPGA AR. Design cycle of FPGA AR is reduced from
months to weeks with the automated standard cell based approach. Besides that,
timing closure is able to cover more timing scenarios. Results show that FPGA AR
using standard cell based approach is meeting the given design specification. IR drop
on both power and ground is achieving less than 2mV per rail, frequency of 330MHz
is obtained on FPGA AR and area size is 0.975mm2. In summary, standard cell
based approach gives designer more time to focus on resolving design issues, and
close the design in more timing scenarios which cover more design corners to
improve variation due to process, voltage and temperature