Design of fpga address register in 28nm process technology based on standard cell based approach
| dc.contributor.author | Choo , Chew Ming | |
| dc.date.accessioned | 2021-04-08T07:52:54Z | |
| dc.date.available | 2021-04-08T07:52:54Z | |
| dc.date.issued | 2013-07-01 | |
| dc.description.abstract | Traditionally, Field Programmable Gate Array (FPGA) Address Register (AR) is designed using full custom approach. With geometries shrink on advance process node, there is a need to reconsider the design approach used to design FPGA AR because of increased design cycle and complexity that lead to more iteration time on closing block timing. Significant design effort and challenges are required in 28nm and beyond when using full custom approach. Therefore, standard cell based approach is used to design the FPGA AR. Design cycle of FPGA AR is reduced from months to weeks with the automated standard cell based approach. Besides that, timing closure is able to cover more timing scenarios. Results show that FPGA AR using standard cell based approach is meeting the given design specification. IR drop on both power and ground is achieving less than 2mV per rail, frequency of 330MHz is obtained on FPGA AR and area size is 0.975mm2. In summary, standard cell based approach gives designer more time to focus on resolving design issues, and close the design in more timing scenarios which cover more design corners to improve variation due to process, voltage and temperature | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/12679 | |
| dc.language.iso | en | en_US |
| dc.title | Design of fpga address register in 28nm process technology based on standard cell based approach | en_US |
| dc.type | Thesis | en_US |
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