Design Of Cmos, Up-Conversion Mixer For Rf Integrated Circuits
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Date
2003-05
Authors
Harikrishnan
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Abstract
The design, analysis and implementation of a high frequency 1-3GHz tunable pure NMOS
Quadrature Up-Conversion mixer topology is presented. The mixer is implemented in a
deep submicron O.25~m CMOS process technology. Utilizing an off-chip tunable inductor
had achieved tunable range of frequency. Various passive components had been
incorporated in the circuitry to increase the linearity of the topology. The mixer, which is a
configuration of a balanced modulator, is composed from a Parallel Structure Low Voltage
Multiplier topology, High Gain Phase Shifting network and a Differential Cascode
amplification stage at the output. Various topology of four quadrant multiplier, biased in
different region of operation had been simulated and analyzed. The utilized topology
requires fewer amounts of stacked transistors, thus reducing the voltage headroom
requirement of the circuitry. The proposed high gain phase shifter relaxes the requirement
of cascading several stages of limiting amplifier at the output. Various layout techniques
such as shielding, matching and transistor splitting had also been implemented in the-layout
in order to reduce the possibilities of chip failure, when installed in the field.
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Keywords
The design, analysis and implementation , of a high frequency 1-3GHz tunable