Design Of Cmos, Up-Conversion Mixer For Rf Integrated Circuits
| dc.contributor.author | Harikrishnan | |
| dc.date.accessioned | 2016-10-24T03:18:46Z | |
| dc.date.available | 2016-10-24T03:18:46Z | |
| dc.date.issued | 2003-05 | |
| dc.description.abstract | The design, analysis and implementation of a high frequency 1-3GHz tunable pure NMOS Quadrature Up-Conversion mixer topology is presented. The mixer is implemented in a deep submicron O.25~m CMOS process technology. Utilizing an off-chip tunable inductor had achieved tunable range of frequency. Various passive components had been incorporated in the circuitry to increase the linearity of the topology. The mixer, which is a configuration of a balanced modulator, is composed from a Parallel Structure Low Voltage Multiplier topology, High Gain Phase Shifting network and a Differential Cascode amplification stage at the output. Various topology of four quadrant multiplier, biased in different region of operation had been simulated and analyzed. The utilized topology requires fewer amounts of stacked transistors, thus reducing the voltage headroom requirement of the circuitry. The proposed high gain phase shifter relaxes the requirement of cascading several stages of limiting amplifier at the output. Various layout techniques such as shielding, matching and transistor splitting had also been implemented in the-layout in order to reduce the possibilities of chip failure, when installed in the field. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/2794 | |
| dc.subject | The design, analysis and implementation | en_US |
| dc.subject | of a high frequency 1-3GHz tunable | en_US |
| dc.title | Design Of Cmos, Up-Conversion Mixer For Rf Integrated Circuits | en_US |
| dc.type | Thesis | en_US |
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