Development Of Spacer Free Self-Aligned Contact Implantation For Power Devices
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Date
2009-11
Authors
Poobalan, Banu
Journal Title
Journal ISSN
Volume Title
Publisher
Universiti Sains Malaysia
Abstract
Optimization of the process integration scheme for a technology is one of the key factors within wafer fabrication in order to reduce defect density and production cycle time. Within this master study, an optimized process flow for the self-aligned contact implantation was evaluated for the Infineons CoolMOS technology. After intensive feasibility investigations of 3 different ideas, the most promising concept was further optimized and characterized on wafer level as well as in the final product. The current technology utilizes side-wall spacers, which are formed by deposition of silicon dioxide followed by an anisotropic oxide etched prior to contact-hole implantation.
Description
Keywords
Spacer Free Self-Aligned Contact Implantation , Power Devices