Development Of Spacer Free Self-Aligned Contact Implantation For Power Devices

dc.contributor.author	Poobalan, Banu
dc.date.accessioned	2018-09-06T02:41:21Z
dc.date.available	2018-09-06T02:41:21Z
dc.date.issued	2009-11
dc.description.abstract	Optimization of the process integration scheme for a technology is one of the key factors within wafer fabrication in order to reduce defect density and production cycle time. Within this master study, an optimized process flow for the self-aligned contact implantation was evaluated for the Infineons CoolMOS technology. After intensive feasibility investigations of 3 different ideas, the most promising concept was further optimized and characterized on wafer level as well as in the final product. The current technology utilizes side-wall spacers, which are formed by deposition of silicon dioxide followed by an anisotropic oxide etched prior to contact-hole implantation.	en_US
dc.identifier.uri	http://hdl.handle.net/123456789/6519
dc.publisher	Universiti Sains Malaysia	en_US
dc.subject	Spacer Free Self-Aligned Contact Implantation	en_US
dc.subject	Power Devices	en_US
dc.title	Development Of Spacer Free Self-Aligned Contact Implantation For Power Devices	en_US
dc.type	Thesis	en_US

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